This invention relates to a circuit for processing an intermediate frequency signal and, in particular, an improved circuit suitable for an automatic frequency tuning (AFT) circuit and a synchronous detector section of a television receiver.
In general, a television receiver requires an AFT circuit for automatically tuning the carrier of a video intermediate frequency signal, which is output from a tuner section, into a predetermined frequency, for example, 58.75 MHz. Conventionally, a pseudo-synchronous detection circuit system equipped with the AFT circuit is used as this type of intermediate frequency processing circuit. In this system, the carrier of a video intermediate frequency signal, which is amplified by an intermediate frequency signal amplifier, is extracted by a limiter. The output of the limiter is FM-detected by the AFT circuit and taken out as an AFT signal. The output of the limiter is also input to a video signal detector and used as a carrier for video signal detection (reproduction).
This type of pseudo-synchronous detection circuit system, though being simpler in its arrangement, is liable to produce a quadrature distortion upon detection and thus produce an undesired buzz beat. For this reason, a PLL synchronous detection circuit system has recently been adopted which utilizes a phase locked loop (PLL) circuit as an intermediate frequency signal processing circuit. In this circuit system, therefore, the output of the voltage-controlled oscillator (VCO) of the PLL circuit is used as a detection signal for a video signal detector. That is, the oscillation output of the VCO is phase-locked onto the itermediate frequency signal. First, a signal which is obtained by 90.degree. phase-shifting the oscillation output of the VCO by virtue of a 90.degree. phase shifter is compared, by a phase comparator, with the output of the intermediate frequency signal amplifier. The output of the phase comparator, including a phase error signal, is convert through a low-pass filter to a DC voltage. The DC voltage is used as a control voltage of the VCO.
The output of the intermediate frequency signal amplifier is input through the limiter to the AFT circuit. The AFT circuit extracts the carrier of the intermediate frequency signal through the 90.degree. phase shifter and bandpass filter. A multiplier is used to multiply this carrier with the intermediate frequency signal, and a result of the multiplication is taken out as an AFT signal through the low-pass filter. That is, the AFT circuit judges whether or not the carrier frequency coincides with the video intermediate frequency.
In this case, however, the performance of the AFT circuit is adversely affected by, for example, an error component of an element, such as the above-mentioned bandpass filter, and an "offsetting" phenomenon inherent in the multiplier. It is, therefore, impossible to exactly and automatically adjust the video intermediate frequency.
There exists a difference or discrepancy between the free-running oscillation frequency of the VCO in the PLL circuit section and the carrier frequency of the video intermediate frequency signal which is output from the intermediate frequency signal amplifier. Since, however, it is necessary to broaden the frequency pull-in range upon synchronization at the PLL circuit, it is impossible to narrow the noise bandwidth. In the PLL circuit, therefore, only the carrier component of the video intermediate frequency signal cannot be reproduced exactly, leaving its sideband components behind. Even in this circuit system, the video signal detector cannot detect an exact video detection.
In order to solve the above-mentioned problem, two low-pass filters, having a different time constant, are used in the PLL circuit. It has been the current practice to switch, once the PLL circuit is phase-locked onto the video intermediate frequency, the time constant of the filter in the loop in a direction in which the noise bandwidth is narrowed. It is, therefore, necessary to provide a change-over switch as well as a judgement circuit for judging whether or not the PLL circuit is brought into a phase-locked state. If such an associated circuit is formed as an IC circuit, a greater number of pins are required, offering a bar to a high density integration.
In order to acquire an initial pull-in range, the PLL circuit is required to set the frequency of the VCO within a broader variable range. With a pull-in noise band narrowed, on the other hand, the PLL circuit should set the frequency of the VCO within a narrower variable range so that the phase jitter component of the VCO output does not overlap the video detection output as a noise. In general, a voltage-controlled crystal oscillator (VCXO) using a crystal resonator is known as a VCO of a smaller phase jitter. Since the VCXO is much narrower in its frequency variable range than the ordinary VCO without the crystal resonator, it has been believed inapplicable to the above-mentioned PLL synchronous detection circuit system. In this type of circuit system, the situation exists under which the PLL circuit cannot set a possible noise bandwidth to be so narrow, in spite of the fact that the PLL circuit is effective to suppress the phase jitters of the VCO. For this reason, the video detection output unavoidably involves a quadrature distortion, noises, etc., presenting a bar to an enhanced video detection performance.
Furthermore, since the bandpass filter of the AFT circuit section is externally provided in this type of circuit system, the number of pins required is increased in spite of an attempted IC version.